Use of multiple etching steps to reduce lateral etch undercut

ABSTRACT

In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer ( 160 ), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion ( 160 X 2 ) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask ( 420 ) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a division of U.S. patent application Ser.No. 10/772,932 filed on Feb. 4, 2004, incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to integrated circuits, and moreparticularly to reducing a lateral etch undercut.

In an integrated circuit fabrication process, a layer of material (e.g.a conductive layer, a dielectric, or a semiconductor layer) can bepatterned by an isotropic etch. A masked isotropic etch may involve anundercut—the etchant may etch the layer laterally under the mask. Theundercut can be undesirable. There is a need to impede or eliminate theundercut etching.

SUMMARY

This section summarizes some features of the invention. Other featuresare described in the subsequent sections. The invention is defined bythe appended claims which are incorporated into this section byreference.

In some embodiments of the present invention, before an isotropic etchof a layer, another etch of the same layer is performed. This other etchcan be anisotropic. This etch attacks a portion of the layer adjacent tothe feature to be formed by the isotropic etch. That portion is entirelyor partially removed by the anisotropic etch. Then the isotropic etchmask is formed to extend beyond the feature over the location of theportion subjected to the anisotropic etch. If that portion was removedentirely, then the isotropic etch mask may completely seal off thefeature to be formed on the side of that portion, so the lateral etchingwill not occur. If that portion was removed only partially, then theisotropic etch mask will not necessarily completely seal off the featureto be formed, but the lateral undercut will be impeded because thepassage to the feature under the isotropic etch mask will be narrowed.

Whether or not the portion has been removed entirely or only partially,the extension of the isotropic etch mask beyond the feature can beshortened.

The invention is not limited to isotropic or anisotropic etches.

Other features and advantages of the invention are described below. Theinvention is defined by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a nonvolatile memory according to oneembodiment of the present invention.

FIGS. 2A, 2B, 2C are top views of the memory of FIG. 1.

FIGS. 2D, 2E, 2F show vertical cross sections of the memory of FIG. 1.

FIGS. 3, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C show vertical cross sectionsof memory structures in the process of fabrication according to someembodiments of the present invention.

FIG. 7A is a top view of a memory structure according to an embodimentof the present invention.

FIG. 7B shows a vertical cross section of a memory structure accordingto an embodiment of the present invention.

FIG. 8A is a top view of a memory structure according to an embodimentof the present invention.

FIGS. 8B, 8C, 8D, 8E, 8F show vertical cross sections of memorystructures according to some embodiments of the present invention.

FIGS. 9, 10 are top views of memory structures according to someembodiments of the present invention.

DESCRIPTION OF SOME EMBODIMENTS

The embodiments described in this section illustrate but do not limitthe invention. The invention is not limited to particular materials,process steps, or dimensions. The invention is defined by the appendedclaims.

FIG. 1 is a circuit diagram of a flash memory array which will be usedto illustrate some embodiments of the present invention. FIG. 2A is atop view showing some features of the memory of FIG. 1. FIG. 2B is a topview of an array area which has contact openings to the wordlines. FIG.2C shows another area near the array boundary, possibly overlapping withthe area of FIG. 2B. FIG. 2D shows a vertical cross section markedY1-Y1′ in FIG. 2A. FIG. 2E shows a vertical cross section marked Y2-Y2′in FIGS. 2B and 2C. FIG. 2F shows a vertical cross section marked Y3-Y3′(FIG. 2C).

The memory is fabricated in and over a P type well 104 (doped P−), asshown in FIGS. 2D, 2E, 2F. Well 104 is formed in a semiconductorsubstrate 106 (e.g. monocrystalline silicon) and isolated from the restof the substrate by an N type region (not shown). Each memory cell 110includes a conductive floating gate 120 insulated from P well 104 bydielectric 130. Control gate 140 overlies the floating gate. Controlgate 140 is part of a conductive control gate line (e.g. polysilicon)that provides control gates for one row of the memory cells. The controlgates are insulated from the underlying floating gates by dielectric150A. In each row, a conductive wordline 160 provides the select gatesfor the memory cells. The wordline 160 is insulated from control gates140 and floating gates 120 by dielectric 170, and from P well 104 bydielectric 180.

Each memory cell 110 has two N+ source/drain regions 190, 200 in P well104. Region 200 (“source line” region), adjacent to floating gate 120,is part of an N+ source line. The source lines run in the row direction(X direction in FIG. 2A). Each source line 200 is shared by two adjacentrows.

In each column of the memory cells, “bitline regions” 190 are connectedto a bitline 220 (FIG. 2D). The bitline is formed from an overlyingconductive layer 224. The contact openings to bitline regions 190 areshown at 230 in FIGS. 2A and 2D.

Isolation trenches 240 (FIGS. 2A, 2B, 2C, 2E, 2F) are formed insubstrate 106 between adjacent columns of the memory cells by a shallowtrench isolation process (STI). Each trench 240 extends across twomemory rows between two respective source lines 200. The trenches arefilled with dielectric. We will use the same numeral 240 for thetrenches and the dielectric filling the trenches. As shown in FIG. 2E,the dielectric totally fills the trenches and projects above thetrenches. In other embodiments, the dielectric is limited to thetrenches, and may or may not totally fill the trenches.

In FIG. 1, each cell 110 is represented as a floating gate transistorand a select gate transistor connected in series. This diagram is not aprecise representation of the memory because the channel regions of thefloating gate transistor and the select transistor are merged together.(The channel region of the floating gate transistor is a P type regionin well 104 under the floating gate 120. The channel region of theselect transistor is a P type region in well 104 under select gate 160.)There is no N type region between the two channel regions. Otherembodiments include an N type region between the two channel regions. Ofnote, some embodiments are non-flash EEPROM memories.

Each wordline 160 is formed as a spacer on a sidewall of a row structure280 which includes dielectric 130, floating gates 120, dielectric 150A,and control gate line 140 for the corresponding row of the memory cells.Row structure (“control gate structure”) 280 also includes a siliconnitride layer 290 formed on top of control gate line 140 to protect thecontrol gate 140 during an etch of wordline layer 160. Nitride 290 isnot shown in FIGS. 2A-2C. Row structure 280 includes dielectric spacers170 separating the control gate line 140 and the floating gates 120 fromwordline 160. Each row structure 280 projects upward over the topsurface of substrate 106 and trench dielectric 240. Dielectric spacers170 form a dielectric sidewall of each control gate structure 280. Thewordline 160 overlies one such sidewall in each row.

Dielectric 310 (FIGS. 2D, 2E, 2F) overlies the control gate structures280 and the wordlines 160. Conductive layer 224 from which the bitlinesare formed overlies the dielectric 310. Dielectric 314 overlies theconductive layer 224. A layer 320 overlies dielectric 314. Contactopenings 330.1 (FIG. 2E) in dielectric 310 and contact openings 330.2 indielectric 314 allow an electrical path to be formed between wordlines160 and layer 320. These openings are shown in FIGS. 2B, 2E at 330.Conductive plugs 224P are formed in openings 330.1. These plugs contactthe wordlines 160. Layer 320 contacts the plugs 224P through openings330.2. In one embodiment, layer 320 is a conductive layer patterned toform strap lines to reduce the resistance between different wordlineportions. Each strap line 320 runs over the corresponding wordline 160and electrically contacts the wordline through openings 330.1, 330.2 atperiodic intervals along the memory row. See U.S. patent applicationSer. No. 09/972,388 filed Oct. 5, 2001 (published as No. 2003/0067806 onApr. 10, 2003), incorporated herein by reference. In some embodiments,the layer 320 has a lower resistivity, a lower sheet resistance, and alower resistance per unit length than the wordline layer 160. Theinvention is not limited to the use of strap lines. Also, in someembodiments, the strap lines are formed on dielectric 310; plugs 224Pare omitted; bitlines 220 overlie the layer 320.

Making contacts to wordlines 160 is facilitated by pedestals 340 (FIGS.2B, 2C, 2E) formed adjacent to control gate structures 280 near contactopenings 330.1. The pedestals project upward over the top surface ofsubstrate 106 and trench dielectric 240. Wordlines 160 overlie thepedestals. At pedestals 340, the wordline does not form a spacer butstretches between the dielectric sidewall 170 of structure 280 and thepedestal and reaches the pedestal. The pedestals change the profile ofthe top surface of wordlines 160 near openings 330.1. The top surface ofthe wordlines is raised up, so the openings 330.1 do not have to be asdeep. Also, the minimum thickness of wordlines 160 is increased near theopenings. The increased thickness counteracts the loss of layer 160during the etch of openings 330.1. Consequently, the etch process marginis increased, the photolithographic alignment tolerances are relaxedwhen the openings are patterned, and the wordline contact resistancetends to be lower.

In the embodiment being described, pedestals 340 are formed from thelayers 150A, 140, 290, 170 used also to form the structures 280. Inother embodiments, pedestals 340 include layers not present instructures 280.

In the embodiment of FIGS. 2A-2F, pedestals 340 are dummy structures,i.e. they do not have any electrical functionality. In particular, theportions of conductive layer 140 in pedestals 340 are dummy elements(having no electrical functionality) rather than circuit elements.

In this embodiment, the wordlines are widened near the openings 330because the distance D1 (FIG. 2B) between the wordline and the adjacentpedestal is greater than the width D2 of the wordline spacer. Thedistance D1 is large enough to accommodate the opening 330. In otherembodiments, the wordlines are not widened near the contact openings.The invention covers embodiments in which the wordlines' width remainsunchanged near the contact openings (D1=D2), and embodiments in whichthe wordlines are narrower near the contact openings (D1<D2). If D1 issmall, the contact openings 330 may overlie the adjacent pedestals 340and/or the control gate lines 140.

In the embodiment of FIGS. 2A-2F, contact openings 330 are located at aboundary of the memory array, in an area where there are no floatinggates. Openings 330 can also be located in gaps in the memory array (seeU.S. Pat. No. 6,355,524 issued Mar. 12, 2002 to Tuan et al., and U.S.patent application Ser. No. 10/402,698 filed Mar. 28, 2003 by Chung etal., both incorporated herein by reference). There are no memory cells(no floating gates) in the gaps. Control gate lines 140 and source lines200 run uninterrupted through the gaps or the array boundary. Placingthe contact openings 330.1, 330.2 in areas with no floating gates isdone to avoid a short between the wordline contacts and the bitlinecontacts in openings 230. These gaps or array boundary areas are formedover STI regions 240. These layout features are optional.

The cross section Y1-Y1′ (FIG. 2A) passes in the Y direction (columndirection) through an active area of a memory cell and through a bitlinecontact opening 230. Cross section Y2-Y2′ (FIGS. 2B, 2C) passes in the Ydirection through a pedestal 340 and a contact opening 330. Crosssection Y3-Y3′ (FIG. 2C) passes in the Y direction near the ends ofcontrol gate lines 140.

In one embodiment, the memory is fabricated as follows. P well 104 isisolated by N type dopant implantation. Dielectric 130 (“tunnel oxide”)is formed on substrate 106. In one embodiment, dielectric 130 is a 9 nmthick layer of silicon dioxide. (The dimensions and materials are givenfor illustration and are not limiting.) A doped polysilicon layer 120 isdeposited on oxide 130. The thickness of layer 120 is 120-200 nm. Then asilicon nitride mask (not shown) is formed on layer 120 to defineisolation trenches 240. Polysilicon 120, oxide 130, and substrate 106are etched where exposed by this mask, so that the isolation trenches240 are formed. Trenches 240 are filled with a suitable dielectric (e.g.silicon dioxide). See FIG. 3 (cross section Y2-Y2′ ). The nitride maskis removed. Optionally, dielectric 240 is etched to lower its top levelbelow the top surface of polysilicon 120.

Isolation regions 240 are also formed in the peripheral area (not shown)during these steps.

Then dielectric layer 150A is formed on polysilicon 120 in the memoryarray area. See FIG. 4A (cross section Y1-Y1′) and FIG. 4B (crosssection Y2-Y2′). Also, polysilicon 120 and oxide 130 are removed in theperiphery, and gate dielectric layer 150P (FIG. 4C) is formed onsubstrate 106 in the peripheral active area for the peripheraltransistors. In one embodiment, dielectric 150A is ONO, i.e. a sandwichof silicon dioxide, silicon nitride, and silicon dioxide. Exemplarythickness values of the oxide, nitride, oxide layers are 30-60 Å, 60-100Å, and 30-60 Å respectively. Dielectric 150P is silicon dioxide. In oneembodiment, before the removal of layers 120 and 130 in the periphery,the first 30-60 Å oxide layer for ONO 150A is formed over the wholewafer, and then the 60-100 Å nitride layer is formed. Then the array. ismasked, and the periphery is etched to remove the nitride layer, theoxide layer, the polysilicon 120, and the oxide 130. Substrate 106becomes exposed in the peripheral active areas (the areas not occupiedby isolation regions 240). Then the array mask is stripped, and asilicon dioxide layer is deposited to over the whole wafer a thicknessof 30-60 Å. This layer provides the top oxide for ONO 150A, and alsoprovides part of the gate oxide 150P for high voltage peripheraltransistors. Then a photoresist mask (not shown) is formed to cover thearray and the high voltage peripheral active areas, and the oxide isetched off from the low voltage peripheral active areas to expose thesubstrate 106. The photoresist is removed, and the structure is oxidizedto grow the gate oxide 150P in the low voltage peripheral active areas,to increase the gate oxide thickness in the high voltage peripheralactive areas, and to slightly increase the oxide thickness at the top ofONO 150A.

Other processes to form the dielectric layers 150A, 150P are alsopossible. The thickness of dielectric 150P can be different fordifferent transistors. For example, a thicker dielectric can be providedfor the high voltage transistors. See the aforementioned U.S. Pat. No.6,355,524.

Doped polysilicon 140 is deposited on dielectric 150A, 150P to athickness of 100-250 nm for example. Silicon nitride 290 is deposited onpolysilicon 140. An exemplary thickness of nitride 290 is 100-300 nm.

A photoresist layer 370 is deposited and patterned to define the controlgate lines 140 and the pedestals 340. Silicon nitride 290 is removedwhere exposed by resist 370. The photoresist can optionally be removed,with the silicon nitride 290 acting as a hard mask. Polysilicon 140 anddielectric 150A are etched away where exposed by nitride 290. Then theexposed portion of polysilicon 120 and some of the underlying dielectric130 are etched away. See FIG. 5A (cross section Y1-Y1′) and FIG. 5B(cross section Y2-Y2′). The periphery is protected by resist 370 duringthe etch of nitride 290, so the periphery remains unchanged.

Resist 370 is removed. The exposed sidewalls of polysilicon layers 120,140 are oxidized, and then thin silicon nitride spacers are formed onthe sidewalls of structures 280, to produce dielectric 170. Dielectric170 also forms on the sidewalls of pedestals 340 (FIG. 5B). The exposedportions of oxide 130 are etched away.

Gate dielectric 180 (silicon dioxide) is grown on substrate 106 for theselect transistors. Polysilicon 160 is deposited over the structure(this can be done by low pressure chemical vapor deposition, i.e.LPCVD), and is heavily doped during or after the deposition. Polysilicon160 fills the areas between the pedestals 340 and the adjacent controlgate structures 280. In some embodiments, the deposition process isconformal, and the thickness of layer 160 exceeds half the distancebetween the pedestal 340 and the adjacent structures 280. In oneembodiment, polysilicon 160 is about 300 nm thick. Pedestals 340 makethe profile of polysilicon 160 more lateral (less sloped) in the areasbetween the pedestals and the structures 280, and the minimumpolysilicon thickness is increased in these areas.

Polysilicon 160 is planar over the peripheral active areas (FIG. 5C)because the underlying layers 290, 140, 150P are planar in these areas.These layers may have a non-planar topography at the boundary betweenthe active areas and the substrate isolation areas (not shown in FIG.5C).

Polysilicon 160 is subjected to an anisotropic, preferentially verticaletch (e.g. reactive ion etching, RIE) without a mask. The lateral etchrate may or may not be zero, but it is less than the vertical etch rate.The etch forms spacers on the sidewalls of structures 280 and pedestals340. See FIG. 6A (cross section Y1-Y1′) and 6B (cross section Y2-Y2′ ).The etch stops on oxide 180 in the active areas of the array.

Polysilicon 160 is entirely removed from the periphery during this etch.See FIG. 6C.

FIG. 7A is a top view of the resulting structure in the memory arrayarea near the pedestals 340. Polysilicon 160 forms sidewall spacers overthe sidewalls of control gate structures 280. Each structure 280 has asidewall 280.1 facing the pedestals 340, the opposite sidewall 280.2,and two end portions 280E at the opposite ends of structure 280 (onlyone end portion 280E is shown in FIG. 7A for each structure 280).Polysilicon layer 160 includes the wordline spacers formed oversidewalls 280.1, and also includes spacers 160X1 over sidewalls 280.2.Spacers 160X1 will be removed as described below. Layer 160 alsoincludes spacers 160X2 at the end portions 280E. Each spacer 160X2 runsaround the end portion 280E and meets the spacer 160X1 and the wordlineportion of polysilicon 160. Some, but not necessarily all, ofpolysilicon 160X2 will be removed, as described below.

Each pedestal 340 physically contacts two adjacent wordlines 160. Theanisotropic etch of polysilicon 160 forms polysilicon spacers 160Earound the edges 340E of pedestals 340. These spacers are marked 160E.Each spacer 160E shorts together two adjacent wordlines 160. This shortwill be eliminated as described below.

A photoresist mask 410 is formed photolithographically over the wafer todefine the gates of the peripheral transistors (FIG. 7B). These gateswill be formed by an anisotropic etch of nitride 290 and polysilicon140. In addition, the mask openings may expose the polysilicon 160E(FIG. 7A). Polysilicon 160E does not have to be completely removed bythe etch through mask 410, but will be removed at least partially, asdescribed in more detail below. The openings over the polysilicon 160Eoverlap the pedestals 340.

Additional mask openings overlie the polysilicon spacers 160X2. Theseopenings overlap the ends 280E of control gate structures 280. At eachend 280E, part of polysilicon 160X2 overlies the sidewall 280.2 (thispart is contiguous with polysilicon spacer 160X1), and another partoverlies the sidewall 280.1 (this part is contiguous with wordline 160).The part of spacer 160X2 over sidewall 280.1 is at least partiallyremoved by the etch through mask 410 in order to protect the wordlinesduring the subsequent isotropic etch of spacers 160X1, as describedbelow.

Nitride 290 (FIG. 7B) and polysilicon 140 are etched anisotropicallythrough the openings in mask 410 to form the peripheral transistorgates. The polysilicon etch attacks the exposed polysilicon 160E, 160X2(FIG. 7A). Also, the nitride and polysilicon etches remove the ends ofcontrol gate structures 280 and pedestals 340. The resulting structureis shown in FIGS. 8A (top view), 8B (periphery), 8D (cross sectionY3-Y3′), and 8E (cross section Y4-Y4′ marked in FIGS. 7A, 8A, passing inthe Y direction through the location of the removed portions of controlgate structures 280). The active areas of the memory cells remainunchanged, as shown in FIG. 8C (cross section Y1-Y1′).

As illustrated in FIG. 8E, dielectric 170 can be partially removed bythe etch of nitride 290.

Polysilicon portions 160E, 160X2 do not have to be completely removedduring the etch of polysilicon 140. Polysilicon spacers 160 can bethicker (taller) than the polysilicon 140, and the etch may terminatebefore the exposed polysilicon 160 is completely removed. In oneembodiment, polysilicon spacers 160 are 240-360 nm thick, andpolysilicon 140 is only 80-200 nm thick. FIG. 8A shows a possibleresidue (“stringers”) of polysilicon 160E as 160S I, and a possibleresidue of polysilicon 160X2 as 160S2. See also FIGS. 8E and 8F. FIG. 8Fshows a cross section X1-X1′ marked in FIG. 8A, passing in the Xdirection through wordline 160 and the polysilicon stringer 160S2.

Due to the etch of polysilicon spacers 160, the spacers become reducedin height, and can also be reduced in width. For example, the width ofspacer 160S2 can be smaller than D2 (FIG. 2B).

Resist 410 is stripped. A photoresist mask 420 (FIGS. 8A-8F) is formedphotolithographically over the wafer to remove the polysilicon 160X1.The mask openings may expose the entire source lines 200 because thesource lines are protected by oxide 180 (FIG. 8C). The edges of the maskopenings are positioned over the adjacent control gate structures 280.

FIG. 9 is the top view of the structure immediately after thepolysilicon etch through mask 420.

Mask 420 also has openings over portions of polysilicon stringers 160S1(FIGS. 8A, 9). The etch removes the exposed polysilicon 160S1 toeliminate the short between the wordlines.

In some embodiments, the polysilicon etch is isotropic. Mask 420 extendsbeyond the ends of wordlines 160 near the control gate structuresidewalls 280.1 (FIGS. 8A, 8F). This is done to prevent the lateral etchof the wordlines under the resist 420. The presence of polysiliconresidue 160S2 under the resist is undesirable because the etchant canremove this residue and reach the wordlines. However, since the residue160S2 has a smaller cross-sectional area than the original polysiliconspacers 160X2 (FIG. 7A), it is more difficult for the etchant to removethe residue and attack the wordlines because the etchant has to workthrough a narrower passage occupied by the residue under the resist.This advantage (a narrower passage) is obtained due to the design ofmask 410 (FIG. 7A) which exposed the polysilicon 160X2 over thesidewalls 280.1.

As shown in FIG. 9, some polysilicon residue 160S1, 160S2 may remain inthe final structure. Polysilicon 160S2 may form an extension of wordline160. This extension may be contiguous with the wordline.

FIGS. 2B, 2C do not show the polysilicon residue. In some embodiments,no reside is left after the etch through mask 410.

Resist 420 covers the entire periphery, so the periphery is not affectedby the etch through mask 420.

The remaining fabrication steps can be similar to those described in theaforementioned U.S. Pat. No. 6,355,524 and U.S. patent application Ser.No. 10/402,698. Briefly, dopant implantation steps are performed tocreate source line regions 200 and bitline regions 190 (FIG. 2A, 2D,2E). Interlayer dielectric (e.g. phosphosilicate glass, PSG) 310 isdeposited over the wafer, and polished back using chemical mechanicalpolishing (CMP). See FIGS. 2D, 2E. Contact openings 230, 330.1 areetched in dielectric 310. Conductive layer 224 (e.g. tungsten) isdeposited and patterned to form bitlines 220 and plugs 224P.

Dielectric 314 is formed over the structure. Contact openings 330.2(FIG. 2E) are etched in dielectric 314. Metal 320 is deposited andpatterned to provide strap lines for wordlines 160.

In an exemplary embodiment, the height of each pedestal 340 is 240-360nm. (The height of pedestals 340 is the combined thickness of layers150, 140, 290). The height of each control gate structure 280 over thetrench dielectric 240 is also 240-360 nm. The initial thickness ofpolysilicon layer 160 is 200-300 nm. After the anisotropic etch thepolysilicon spacers 160 are at most as high as the structures 280 insome embodiments. Therefore, in the area of trenches 240, the spacers160 are at most 240-360 nm in height. In the area of pedestals 240, theminimal thickness of wordlines 160 is 60-200 nm. The etch of openings330.1 is therefore shortened.

FIG. 10 illustrates another embodiment. Masks 410, 420 have the samegeometry in the array area as in FIGS. 7A, 8A, but the etch through mask410 is not used to pattern the peripheral transistor gates. The etchthrough mask 410 etches the polysilicon but not the silicon nitride.Control gate structures 280 and the pedestals 340 are protected bynitride 290 and hence are not affected by this etch.

The structure of FIG. 10 can also be obtained if the etch through mask410 patterns the peripheral transistor gates but the nitride 290 isremoved from the periphery before this etch.

The invention is not limited to the embodiments described above. Theinvention is not limited to the particular materials, process parametersor layer thicknesses. The etch through mask 420 may pattern thewordlines only partially, with the final patterning accomplished bysubsequent etches. The invention is applicable to other memory circuitsand memory cell structures. For example, isolation trenches 240 areoptional. Other isolation techniques can be used (e.g. LOCOS). Further,the memory may have no control gates. See R. Mih et al., “0.18 umModular Triple Self-Aligned Embedded Split-Gate Flash Memory”, 2000Symposium on VLSI Technology, Digest of Technical Papers, pages 120-121incorporated herein by reference. FIGS. 2B and 2C show a single contactopening 330 at each pedestal 340, but the memory may contain any numberof the openings 330 at each pedestal. Openings 330 can be provided onboth sides of the pedestal to contact the two respective wordlines. Thememory may be programmed or erased through P well 104 or wordlines 160or by other mechanisms, known or to be invented. Other embodiments andvariations are within the scope of the invention, as defined by theappended claims.

1. An integrated circuit comprising: a first feature; and an extensionof the fist feature, the extension being formed from the same materialas the first feature, the extension being contiguous with the firstfeature, the extension having a smaller cross sectional area than thefirst feature.
 2. The integrated circuit of claim 1 further comprising asemiconductor substrate, and a first structure projecting upward overthe semiconductor substrate, the first structure comprising a firstsidewall; wherein the first feature overlays the first sidewall of thefirst structure.
 3. The integrated circuit of claim 2 wherein theextension of the first feature does not project upward as far as thefirst feature.
 4. The integrated circuit of claim 1 wherein the firstfeature and the extension are sidewall spacers on the first sidewall. 5.The integrated circuit of claim 1 wherein the first feature and theextension are conductive.
 6. The integrated circuit of claim 1 whereinthe first structure comprises a conductive line, and the first sidewallis dielectric.
 7. The integrated circuit of claim 6 wherein theconductive line provides control gates to a plurality of memory cells,the first structure also comprises conductive floating gates of thememory cells, and the first feature is a wordline for the memory cells.